The present invention generally relates to a nonvolatile semiconductor memory device, and more particularly relates to an electrically erasable and programmable read only memory (EEPROM).
A flash EEPROM (flash memory), which can erase data at a time on a block-by-block basis, is known in the art. An n-channel memory cell transistor, including control gate (CG), floating gate (FG), drain and source, for example, is used for the flash memory. In a program cycle, electrons are stored on the floating gate by a hot electron injection mechanism, and the memory cell transistor (which will be herein called MCT) has a relatively high threshold voltage. The MCT that has stored data xe2x80x9c1xe2x80x9d thereon in this manner is herein defined as being in xe2x80x9cOFF statexe2x80x9d. In an erase cycle, electrons are removed from the floating gate, and the MCT has a relatively low threshold voltage. The MCT that has stored data xe2x80x9c0xe2x80x9d thereon in this way is herein defined as being in xe2x80x9cON statexe2x80x9d. In a read cycle, a predetermined gate voltage is applied between the control gate and source while the drain and source are supplied with positive low potential and ground potential, respectively.
A differential sensing flash memory that can perform a high-speed read operation is also known. This flash memory includes a dummy cell transistor (which will be herein called DCT) and a differential sense amplifier to read data from an MCT thereof. The DCT has the same construction as the MCT and is turned ON beforehand. The drains of the MCT and DCT are connected to the differential sense amplifier via a bit line and a reference line, respectively. In a read cycle, the drain current of the DCT is adjusted to half of the drain current of the MCT in the ON state. The differential sense amplifier compares a bit line voltage with a reference voltage, thereby sensing the state of the MCT. The bit line and reference voltages are variable with the drain currents of the MCT and DCT, respectively.
This construction, however, causes a phenomenon called xe2x80x9cRDD (read drain disturb)xe2x80x9d. Specifically, as the read cycle operations are repeatedly performed, some hot electrons are adversely injected into the floating gate of the DCT. As a result, the threshold voltage of the DCT rises and its drain current decreases.
To solve this problem, the DCT is replaced by a single-gate NMOS transistor, in which no hot electrons can be injected into the floating gate, according to the technique disclosed in Japanese Laid-Open Publication 9-320283. The gate voltage applied to the gate of the NMOS transistor (i.e., reference transistor) is obtained by dividing a voltage with magnitude approximately equal to that of the gate voltage applied to the control gate of the MCT using capacitive divider.
The drain current of an MCT, including control gate and floating gate, and the drain current of a single-gate NMOS transistor show mutually different temperature dependence. Also, even if fabricating process conditions have changed in the same way the drain current characteristics of these transistors change differently in response to the variation. Therefore, according to the technique disclosed in the above-identified publication, it is impossible to change the reference voltage of the NMOS transistor as a reference transistor in accordance with the actual temperature dependence of the MCT and the variation in drain current characteristic of the MCT resulting from the variation of process conditions.
It is therefore an object of the present invention to provide a nonvolatile semiconductor memory device that ensures accurate and high-speed read operation even if temperature or fabricating process conditions have changed.
To achieve this object, the present invention provides a nonvolatile semiconductor memory device that is so constructed as to read data stored on a memory cell transistor with a floating gate by a differential sensing method. The device of the invention is characterized by generating a gate voltage for a reference transistor in accordance with the drain current characteristic of a dummy cell transistor. For this purpose, the inventive device is provided with a gate voltage generator including: a dummy cell transistor that has the same construction as the memory cell transistor; a current mirror for creating a current proportional to a drain current of the dummy cell transistor; and transistor means for generating a gate voltage for the reference transistor in accordance with the current created by the current mirror.